With constant down-scaling and increasingly demanding requirements to the speed and functionality of ultra-high density integrated circuits, conventional planar metal-oxide-semiconductor field effect transistors (MOSFETs) face increasing challenges with such issues as scaling of gate oxide thickness and electrostatic control of the gate electrode over the channel region. Fin field effect transistors (FinFETs) have exhibited improved control over a planar gate MOSFET design by wrapping the gate electrode over three sides of a fin-shaped channel.
GAA MOSFETs are similar to FinFETs but have the potential of even greater electrostatic control over the channel because the gate electrode completely surrounds the channel. In a GAA MOSFET, the channel region is essentially a nanowire. The nanowire channel typically has a thickness (or diameter) in the tens of nanometers (nm) or less and has an unconstrained length. The nanowire channel is suspended generally horizontally between, and anchored to, the much larger source and drain regions of the GAA MOSFET.
GAA MOSFETs can be fabricated on a bulk silicon substrate utilizing fully compatible CMOS technology. A typical manufacturing method of forming the channel regions in a GAA MOSFET involves epitaxially growing a stack (epi-stack) of sacrificial layers sandwiched between channel layers on top of a bulk substrate. The sacrificial layers and channel layers are composed of two different materials so that selective etching can remove the sacrificial layers.
By way of example, an epi-stack can be formed of alternating silicon (Si) and silicon germanium (SiGe) layers, wherein the Si layers are the sacrificial layers and the SiGe layers are the channel layers. The Si layers can then be removed by selective etching (for example via a wet etching process such as a TMAH), which also inadvertently recesses trenches into the bulk substrate due to the similarity of materials composing the sacrificial layers and the substrate. The SiGe layers can subsequently be formed into the nanowire channels suspended over the trenches. A thin gate dielectric is then disposed around the SiGe nanowire channels and over the recessed trenches of the substrate. Metal is then disposed over the dielectric to form the metal gate electrode of the GAA MOSFET.
Problematically however, it is difficult to control the inadvertent etching of the recessed trenches under the nanowire channels. This uncontrolled etch introduces trench to trench variations and an undesired roughness at the bottoms of the trenches, which can detrimentally affect device performance. Additionally, the thin gate dielectric deposition does not always sufficiently isolate the metal gate from the substrate, which can lead to shorts across the gate dielectric from electrode to substrate.
Accordingly, there is a need for a method of forming nanowire channels in GAA MOSFETs, which provides better control of the etching process during removal of sacrificial layers with little or no trench formation. Moreover, there is a need for a method of forming nanowire channels, which prevents electrical shorts across the gate dielectric.